xilinx.com project coregen 1.0 clk_B clk_B true true false false false No_Jitter false false 16 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 625.0 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 16 2.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin empty true DONE true false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 1 4 false 62.500 FIXED SYSTEM_SYNCHRONOUS 1 1X false CLK0 CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 4 0.000 CLKFBOUT 1 10.000 SYSTEM_SYNCHRONOUS 0.010 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 0 0 0 0 0 0 clk_B lin 1 1 0.010 0.010 No_Jitter 0 0 0 0 0 0 0 0 DCM_SP 0 16 Units_MHz 100.000 FDBK_AUTO Single_ended_clock_capable_pin Single_ended_clock_capable_pin SINGLE 1 1 0 0 0 0 0 1 BUFG BUFG BUFG BUFG BUFG BUFG BUFG __primary______________16____________0.010 no_secondary_input_clock CLK_OUT1____16.000______1.000______50.0______200.000____150.000 no_CLK_OUT2_output no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 16 100.000 100.000 100.000 100.000 100.000 100.000 2.000 0.000 0.000 0.000 0.000 0.000 0.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 16.000 N/A N/A N/A N/A N/A N/A 2.000 N/A N/A N/A N/A N/A N/A 50.0 N/A N/A N/A N/A N/A N/A None OPTIMIZED 4.000 10.000 10.000 FALSE FALSE ZHOLD 1 0.010 0.010 FALSE 4.000 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE None OPTIMIZED CLKFBOUT 4 10.000 SYSTEM_SYNCHRONOUS 1 0.010 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 None 2.000 1 4 FALSE 62.5 FIXED 1X CLKOUT1 SYSTEM_SYNCHRONOUS 1 FALSE CLK0 NONE NONE NONE NONE NONE None 2 1 4 62.5 0.000 NONE FALSE CLKFX NONE NONE AUTO 0 0 0 0 NONE CLK_IN1 CLK_IN2 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 RESET LOCKED CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N POWER_DOWN DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED 625.0 100.0 MMCM CENTER_HIGH 4000 coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral Verilog false 2012-05-10+12:44 customization_generator model_parameter_resolution_generator ip_xco_generator ./clk_B.xco xco Sat Mar 17 08:49:24 GMT 2018 0x1E82769B generationID_706127423 tcl_flow_generator ./clk_B/example_design/clk_B_exdes.ucf ignore ucf Sat Mar 17 08:49:31 GMT 2018 0x0B91A27B generationID_706127423 ./clk_B/example_design/clk_B_exdes.v ignore verilog Sat Mar 17 08:49:26 GMT 2018 0x0A61380D generationID_706127423 ./clk_B/example_design/clk_B_exdes.xdc ignore xdc Sat Mar 17 08:49:31 GMT 2018 0xC46CA9FD generationID_706127423 ./clk_B/implement/implement.bat ignore unknown Sat Mar 17 08:49:31 GMT 2018 0xBC516876 generationID_706127423 ./clk_B/implement/implement.sh ignore unknown Sat Mar 17 08:49:31 GMT 2018 0x4C5CE61A generationID_706127423 ./clk_B/implement/planAhead_ise.bat ignore unknown Sat Mar 17 08:49:30 GMT 2018 0x6966A508 generationID_706127423 ./clk_B/implement/planAhead_ise.sh ignore unknown Sat Mar 17 08:49:30 GMT 2018 0x7F8B5943 generationID_706127423 ./clk_B/implement/planAhead_ise.tcl ignore tcl Sat Mar 17 08:49:30 GMT 2018 0x04EE3F2B generationID_706127423 ./clk_B/implement/planAhead_rdn.bat ignore unknown Sat Mar 17 08:49:30 GMT 2018 0xB9373CFA generationID_706127423 ./clk_B/implement/planAhead_rdn.sh ignore unknown Sat Mar 17 08:49:30 GMT 2018 0xDCE9D96C generationID_706127423 ./clk_B/implement/planAhead_rdn.tcl ignore tcl Sat Mar 17 08:49:31 GMT 2018 0x4F682C1A generationID_706127423 ./clk_B/implement/xst.prj ignore unknown Sat Mar 17 08:49:31 GMT 2018 0xC1BCF84A generationID_706127423 ./clk_B/implement/xst.scr ignore unknown Sat Mar 17 08:49:32 GMT 2018 0x4829709D generationID_706127423 ./clk_B/simulation/clk_B_tb.v ignore verilog Sat Mar 17 08:49:27 GMT 2018 0xAFDABD4D generationID_706127423 ./clk_B/simulation/functional/simcmds.tcl ignore tcl Sat Mar 17 08:49:29 GMT 2018 0x73B3482B generationID_706127423 ./clk_B/simulation/functional/simulate_isim.bat ignore unknown Sat Mar 17 08:49:29 GMT 2018 0xAFFC48F5 generationID_706127423 ./clk_B/simulation/functional/simulate_isim.sh ignore unknown Sat Mar 17 08:49:29 GMT 2018 0xCBF9C023 generationID_706127423 ./clk_B/simulation/functional/simulate_mti.bat ignore unknown Sat Mar 17 08:49:28 GMT 2018 0xB6465FAB generationID_706127423 ./clk_B/simulation/functional/simulate_mti.do ignore unknown Sat Mar 17 08:49:28 GMT 2018 0x17FDDCC7 generationID_706127423 ./clk_B/simulation/functional/simulate_mti.sh ignore unknown Sat Mar 17 08:49:28 GMT 2018 0x3523E965 generationID_706127423 ./clk_B/simulation/functional/simulate_ncsim.sh ignore unknown Sat Mar 17 08:49:28 GMT 2018 0x73A046BD generationID_706127423 ./clk_B/simulation/functional/simulate_vcs.sh ignore unknown Sat Mar 17 08:49:29 GMT 2018 0x01A9BF75 generationID_706127423 ./clk_B/simulation/functional/ucli_commands.key ignore unknown Sat Mar 17 08:49:29 GMT 2018 0xE69CCC2C generationID_706127423 ./clk_B/simulation/functional/vcs_session.tcl ignore tcl Sat Mar 17 08:49:30 GMT 2018 0xEC91E7B1 generationID_706127423 ./clk_B/simulation/functional/wave.do ignore unknown Sat Mar 17 08:49:28 GMT 2018 0xBD478C70 generationID_706127423 ./clk_B/simulation/functional/wave.sv ignore unknown Sat Mar 17 08:49:29 GMT 2018 0x4B06A970 generationID_706127423 ./clk_B/simulation/timing/clk_B_tb.v ignore verilog Sat Mar 17 08:49:27 GMT 2018 0x7EF392A8 generationID_706127423 ./clk_B/simulation/timing/sdf_cmd_file ignore unknown Sat Mar 17 08:49:29 GMT 2018 0xABDE77D7 generationID_706127423 ./clk_B/simulation/timing/simcmds.tcl ignore tcl Sat Mar 17 08:49:29 GMT 2018 0x3A045FF0 generationID_706127423 ./clk_B/simulation/timing/simulate_isim.sh ignore unknown Sat Mar 17 08:49:29 GMT 2018 0x4568B218 generationID_706127423 ./clk_B/simulation/timing/simulate_mti.bat ignore unknown Sat Mar 17 08:49:28 GMT 2018 0x106970B1 generationID_706127423 ./clk_B/simulation/timing/simulate_mti.do ignore unknown Sat Mar 17 08:49:28 GMT 2018 0xA9E31DFE generationID_706127423 ./clk_B/simulation/timing/simulate_mti.sh ignore unknown Sat Mar 17 08:49:28 GMT 2018 0xFB1991CC generationID_706127423 ./clk_B/simulation/timing/simulate_ncsim.sh ignore unknown Sat Mar 17 08:49:29 GMT 2018 0xBAEF9CF4 generationID_706127423 ./clk_B/simulation/timing/simulate_vcs.sh ignore unknown Sat Mar 17 08:49:30 GMT 2018 0x45826D14 generationID_706127423 ./clk_B/simulation/timing/ucli_commands.key ignore unknown Sat Mar 17 08:49:30 GMT 2018 0x9DC0E037 generationID_706127423 ./clk_B/simulation/timing/vcs_session.tcl ignore tcl Sat Mar 17 08:49:30 GMT 2018 0x28340249 generationID_706127423 ./clk_B/simulation/timing/wave.do ignore unknown Sat Mar 17 08:49:28 GMT 2018 0xE07B101A generationID_706127423 ./clk_B.ucf ucf Sat Mar 17 08:49:31 GMT 2018 0x869625B1 generationID_706127423 ./clk_B.v verilog Sat Mar 17 08:49:26 GMT 2018 0xAA1A1A18 generationID_706127423 ./clk_B.veo veo Sat Mar 17 08:49:27 GMT 2018 0x78E4ED9D generationID_706127423 ./clk_B.xdc ignore xdc Sat Mar 17 08:49:31 GMT 2018 0x5109DC24 generationID_706127423 ./clk_B_xmdf.tcl tcl Sat Mar 17 08:49:27 GMT 2018 0x2A109255 generationID_706127423 associated_files_generator ./clk_B/clk_wiz_v3_6_readme.txt ignore txt Sun Oct 13 18:34:18 GMT 2013 0x5B63DA78 generationID_706127423 ejava_generator ./clk_B/example_design/clk_B_exdes.ucf ignore ucf Sat Mar 17 08:49:33 GMT 2018 0x0B91A27B generationID_706127423 ./clk_B/example_design/clk_B_exdes.v ignore verilog Sat Mar 17 08:49:32 GMT 2018 0x0A61380D generationID_706127423 ./clk_B/example_design/clk_B_exdes.xdc ignore xdc Sat Mar 17 08:49:33 GMT 2018 0xC46CA9FD generationID_706127423 ./clk_B/implement/implement.bat ignore unknown Sat Mar 17 08:49:32 GMT 2018 0xBC516876 generationID_706127423 ./clk_B/implement/implement.sh ignore unknown Sat Mar 17 08:49:32 GMT 2018 0x4C5CE61A generationID_706127423 ./clk_B/implement/planAhead_ise.bat ignore unknown Sat Mar 17 08:49:32 GMT 2018 0x6966A508 generationID_706127423 ./clk_B/implement/planAhead_ise.sh ignore unknown Sat Mar 17 08:49:32 GMT 2018 0x7F8B5943 generationID_706127423 ./clk_B/implement/planAhead_ise.tcl ignore tcl Sat Mar 17 08:49:32 GMT 2018 0x04EE3F2B generationID_706127423 ./clk_B/implement/planAhead_rdn.bat ignore unknown Sat Mar 17 08:49:32 GMT 2018 0xB9373CFA generationID_706127423 ./clk_B/implement/planAhead_rdn.sh ignore unknown Sat Mar 17 08:49:32 GMT 2018 0xDCE9D96C generationID_706127423 ./clk_B/implement/planAhead_rdn.tcl ignore tcl Sat Mar 17 08:49:32 GMT 2018 0x4F682C1A generationID_706127423 ./clk_B/implement/xst.prj ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xC1BCF84A generationID_706127423 ./clk_B/implement/xst.scr ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x4829709D generationID_706127423 ./clk_B/simulation/clk_B_tb.v ignore verilog Sat Mar 17 08:49:33 GMT 2018 0xAFDABD4D generationID_706127423 ./clk_B/simulation/functional/simcmds.tcl ignore tcl Sat Mar 17 08:49:32 GMT 2018 0x73B3482B generationID_706127423 ./clk_B/simulation/functional/simulate_isim.bat ignore unknown Sat Mar 17 08:49:32 GMT 2018 0xAFFC48F5 generationID_706127423 ./clk_B/simulation/functional/simulate_isim.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xCBF9C023 generationID_706127423 ./clk_B/simulation/functional/simulate_mti.bat ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xB6465FAB generationID_706127423 ./clk_B/simulation/functional/simulate_mti.do ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x17FDDCC7 generationID_706127423 ./clk_B/simulation/functional/simulate_mti.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x3523E965 generationID_706127423 ./clk_B/simulation/functional/simulate_ncsim.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x73A046BD generationID_706127423 ./clk_B/simulation/functional/simulate_vcs.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x01A9BF75 generationID_706127423 ./clk_B/simulation/functional/ucli_commands.key ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xE69CCC2C generationID_706127423 ./clk_B/simulation/functional/vcs_session.tcl ignore tcl Sat Mar 17 08:49:33 GMT 2018 0xEC91E7B1 generationID_706127423 ./clk_B/simulation/functional/wave.do ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xBD478C70 generationID_706127423 ./clk_B/simulation/functional/wave.sv ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x4B06A970 generationID_706127423 ./clk_B/simulation/timing/clk_B_tb.v ignore verilog Sat Mar 17 08:49:33 GMT 2018 0x7EF392A8 generationID_706127423 ./clk_B/simulation/timing/sdf_cmd_file ignore unknown Sat Mar 17 08:49:32 GMT 2018 0xABDE77D7 generationID_706127423 ./clk_B/simulation/timing/simcmds.tcl ignore tcl Sat Mar 17 08:49:32 GMT 2018 0x3A045FF0 generationID_706127423 ./clk_B/simulation/timing/simulate_isim.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x4568B218 generationID_706127423 ./clk_B/simulation/timing/simulate_mti.bat ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x106970B1 generationID_706127423 ./clk_B/simulation/timing/simulate_mti.do ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xA9E31DFE generationID_706127423 ./clk_B/simulation/timing/simulate_mti.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xFB1991CC generationID_706127423 ./clk_B/simulation/timing/simulate_ncsim.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xBAEF9CF4 generationID_706127423 ./clk_B/simulation/timing/simulate_vcs.sh ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x45826D14 generationID_706127423 ./clk_B/simulation/timing/ucli_commands.key ignore unknown Sat Mar 17 08:49:33 GMT 2018 0x9DC0E037 generationID_706127423 ./clk_B/simulation/timing/vcs_session.tcl ignore tcl Sat Mar 17 08:49:33 GMT 2018 0x28340249 generationID_706127423 ./clk_B/simulation/timing/wave.do ignore unknown Sat Mar 17 08:49:33 GMT 2018 0xE07B101A generationID_706127423 ./clk_B.ucf ucf Sat Mar 17 08:49:33 GMT 2018 0x869625B1 generationID_706127423 ./clk_B.v verilog Sat Mar 17 08:49:32 GMT 2018 0xAA1A1A18 generationID_706127423 ./clk_B.veo veo Sat Mar 17 08:49:33 GMT 2018 0x78E4ED9D generationID_706127423 ./clk_B.xdc ignore xdc Sat Mar 17 08:49:33 GMT 2018 0x5109DC24 generationID_706127423 ./clk_B_xmdf.tcl tcl Sat Mar 17 08:49:33 GMT 2018 0x2A109255 generationID_706127423 all_documents_generator ./clk_B/doc/clk_wiz_v3_6_readme.txt ignore txt Sat Mar 17 08:49:37 GMT 2018 0x5B63DA78 generationID_706127423 ./clk_B/doc/clk_wiz_v3_6_vinfo.html ignore unknown Sat Mar 17 08:49:37 GMT 2018 0xF2E77607 generationID_706127423 ./clk_B/doc/pg065_clk_wiz.pdf ignore pdf Sat Mar 17 08:49:37 GMT 2018 0xCE1EE896 generationID_706127423 readme_documents_generator asy_generator ./clk_B.asy asy Sat Mar 17 08:49:41 GMT 2018 0xB56352CD generationID_706127423 ise_generator ./clk_B.gise ignore gise Sat Mar 17 08:49:50 GMT 2018 0xEBB5987B generationID_706127423 ./clk_B.xise ignore xise Sat Mar 17 08:49:50 GMT 2018 0xFFD9508B generationID_706127423 deliver_readme_generator flist_generator ./clk_B_flist.txt ignore txtFlist txt Sat Mar 17 08:49:50 GMT 2018 0x61897FCA generationID_706127423 view_readme_generator clk_C clk_C true true false false false No_Jitter false false 16 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 625.0 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 16 5 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin empty true DONE true false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 1 4 false 62.500 FIXED SYSTEM_SYNCHRONOUS 4 1X false CLK0 CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 4 0.000 CLKFBOUT 1 10.000 SYSTEM_SYNCHRONOUS 0.010 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 clk_C coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral Verilog false 2012-05-10+12:44 clk_base clk_base true true false false false No_Jitter false false 50 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 200.0 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 16 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin empty true DONE true false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 25 8 false 20.000 NONE SYSTEM_SYNCHRONOUS 0 1X false CLKFX CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 8 0.000 CLKFBOUT 1 20.0 SYSTEM_SYNCHRONOUS 0.010 128 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 clk_base coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral Verilog false 2012-05-10+12:44 coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -2 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral Verilog false