// refresh with REFRESH parameter after loading black white data
`include "clk_convert.v"
module eink_75(clk, clk_eink, BUSY, BUT1, BUT2, LED1, LED2, DC, CS, DIN, RST);

input clk;
input BUT1;
input BUT2;
input BUSY;
output DC;
output CS;
output DIN;
output RST;
output clk_eink;
output LED1;
output LED2;

clk_convert CLK_CONVERT(clk, clk_eink);

reg dc_r;
reg din_r;
reg rst_r = 1'b1;
reg led1_r = 1'b0;
reg led2_r = 1'b0;
assign DIN = din_r;
assign DC = dc_r;
assign RST = rst_r;
assign LED1 = led1_r;
assign LED2 = led2_r;

// Club 2 below for creating hex
// 2 frames : black 0 and white 1 , white 1 and red 0

parameter WIDTH=80;
parameter HEIGHT=48;

// command and data bits of 7.5 inch 3 color eink
parameter OFF=8'h02;
parameter ON=8'h04;
parameter FREQ=8'h30;
parameter FREQD=8'h0F;			// 1111 denotes 200Hz
parameter SLEEP=8'h07;
parameter SLEEPD=8'hA5;			// To exit deep sleep mode, send HWRESET to the DRIVER
parameter RES=8'h61;						// refer datasheet for 32 data bits.
parameter BLACK=8'h10;						// writes black command bits
parameter RED=8'h13;						// writes red command bits
parameter REFRESH=8'h12;

reg [2*WIDTH*HEIGHT - 1:0] frame;
reg [19:0] datacounter=16'hFFFF;

reg [7:0] push;							// shift register for pushing 8 bits at a time to eink
reg [7:0] pushcount=8'h00;

//reg feed = 1'b0;

// For switching on or off

//refill push to feed image		problem in the loop below
reg powered=1'b0;
always @(posedge clk_eink)
begin
	if (BUT1==0)
	begin
		dc_r=1'b0;					// writes command in 0 state
		if (powered == 1'b0)
		begin
			push = ON;
			pushcount = 8'hFF;
			led1_r = 1'b1;
		end
		else if (powered == 1'b1)
		begin
			push = OFF;
			pushcount = 8'hFF;
			led1_r = 1'b0;
		end
		powered = ~powered;
	end

	else if (BUT2==0)
	begin
//		if (empty && datacounter==16'hFFFF)
//		begin
			frame = {{WIDTH*HEIGHT{1'b0}} ,{WIDTH*HEIGHT{1'b1}} };
			datacounter = 16'h0000;
//		end
	end

	else if (empty && datacounter<=16'h1E10)
	begin
		pushcount = 8'hFF;
		if (datacounter==16'h0000) begin
			dc_r = 1'b0;
			push = BLACK;
			datacounter = 16'h0008;
		end
		else if (datacounter==16'h0F08) begin
			dc_r = 1'b0;
			push = RED;
			led2_r = 1'b1;
			datacounter = datacounter + 16'h0008;
		end
		else if (datacounter==16'h1E10) begin
			dc_r = 1'b0;
			push = REFRESH;
			datacounter = 16'hFFFF;
		end
		else begin
			dc_r = 1'b1;
			push = frame[2*WIDTH*HEIGHT - 1 : 2*WIDTH*HEIGHT - 8];
			datacounter = datacounter + 16'h0008;
			frame = frame<<8;
		end
	end

	else if (~empty && BUSY)
	begin
		din_r = push[7];
		push = push<<1;
		pushcount = pushcount<<1;
	end
end

wire empty;
assign empty = !(|pushcount);
assign CS = empty;					//cs should be made high for 1 cycle after 8 clock cycles

//BUSY is input signal for FPGA
endmodule