module eink(red, black, clk_24khz, DC, CS, DIN, RST, BUSY);

input red, black, clk_24khz;
output DC, CS, DIN, RST, BUSY, eink_clk;

reg dc_r, cs_r, din_r, rst_r, busy_r;

reg [4:0] counter = 5'b0;

//1st step
reg [7:0] sw_reset_c = 8'h12;
//BUSY HIGH
//wait 10 ms

reg [7:0] driver_output_c = 8'h01;
reg [23:0] driver_d = 24'hC70001;

reg [7:0] data_entry_c = 8'h11;
reg [7:0] entry_d = 8'h01;

reg [7:0] ram_sec_c = 8'h44;
reg [7:0] ram_sec_d = 8'h0018;

reg [7:0] ram_sep_c = 8'h45;
reg [31:0] ram_sep_d = 32'hC7000000;

reg [7:0] border_c = 8'h3C;
reg [7:0] border_d = 8'h05;

reg [7:0] ram_acx_c = 8'h4E;
reg [7:0] ram_acx_d = 8'h00;

reg [7:0] ram_acy_c = 8'h4F;
reg [7:0] ram_acy_d = 8'hC700;

reg [7:0] black_c = 8'h10;
reg [40000:0] screen_black=black;		//200x200/16 = 2500
reg [7:0] red_c = 8'h13;
reg [40000:0] screen_red=red;

reg [7:0] sleep_c = 8'h10;
//BUSY high

assign DIN = din_r;
assign CS = cs_r;
assign DC = dc_r;
assign RST = rst_r;
assign BUSY = busy_r;

always @(red or black)
begin
	CS=1'b0;
	counter = 14'b0;
end

always @(posedge clk_24khz)
	counter = counter + 1;

always @(!CS && posedge clk_24khz)
begin
	din_r = ;
end

endmodule